1. Field of the Invention
The present invention relates in general to a method and an apparatus for accessing a pipelined color palette in a color graphics system and in particular to a method and apparatus for selectively accessing a pipelined color palette synchronously when the palette is being used for refreshing a color monitor and asynchronously when the palette is being updated by a central processing unit.
2. Description of Prior Art
A pipelined graphics color palette, also known as a color table look-up memory, comprises a random access memory (RAM) in which there is provided a plurality of storage locations for storing a plurality of words wherein each word defines a particular color to be displayed on a color monitor.
In a typical color graphics system, the palette is coupled to an address register and a data register and access to the palette is required when the palette is being used for refreshing the color monitor during a refresh mode and when the contents of the palette are being updated by a central processing unit (CPU) during a palette update mode.
In addition to the color palette, the address register, the data register, the CPU and the color monitor, there is also provided in the typical color graphics system a video display memory, a shift register, a multiplexer, a plurality of digital-to-analog converters (DAC's) which are coupled to one or more electron guns in the monitor and a video timing generator for providing a pixel clock.
The typical color graphics system is selectively operable in either of two modes: a refresh mode or a palette update mode.
For use in the refresh mode, there is stored in the video display memory a plurality of words. Each of the words corresponds to a separate triad of red, blue and green pixels on the monitor screen and comprises an address of one of the words stored in the color palette.
In the refresh mode, the words stored in the display memory are read out of the display memory into the shift register and from the shift register, via a video address bus, through the multiplexer, into the address register. Control signals for switching the multiplexer are provided by the CPU. As each word from the display memory enters the address register, the word is used for addressing one of the words in the color palette.
The words addressed in the color palette are then read out to the data register. From the data register, the words are transferred to the DAC's. In the DAC's, the words are converted to analog signals. The analog signals are then used to control the outputs of the electron guns while the guns are scanning the triads on the monitor. Controlling the guns controls the intensity of each pixel in the triads and therefore the color of the triads.
The above-described operations of transferring addresses from the display memory to the address register for addressing the color palette, and the transferring of words from the palette to the data register and then to the DAC's for refreshing the monitor are synchronized with the pixel clock in a pipeline manner. That is, in response to each pixel clock pulse, a word is read out of the color palette into the data register and the DAC's and, at the same time in response to the same clock pulse, a new word from the display memory is read into the address register to address the color palette.
In the color palette update mode, addresses from the CPU are transferred via a CPU system address bus through the multiplexer to the address register for addressing the palette and data words are transferred between the CPU and the palette on a CPU system data bus for changing the colors in the palette. At the same time, the CPU provides chip enable and read/write control signals for controlling the data transfers into and out of the palette.
Heretofore, the addressing of and data transfers to and from the palette using CPU addresses in the palette update mode required that the CPU addresses and CPU data transfers be synchronized with either pixel clock pulses used during the refresh mode or with CPU system clock pulses used in normal CPU data transfers.
It has been found that the use of either the pixel clock or the CPU clock for synchronizing CPU addressing and data transfers between the CPU and the color palette has certain disadvantages.
One of the disadvantages found is that synchronized address inputs to the color palette address register in general must meet specified set-up and hold times.
When using the pixel clock, there is another disadvantage. Because the CPU system clock and the typical pixel clock comprise considerably different pulse rates, a complex CPU address synchronizer is required when using the pixel clock.
To avoid using the pixel clock and the required synchronizer, it has been proposed to use the CPU system clock. However, one of the disadvantages of using the CPU system clock is that switching between the pixel and system clocks can result in a loss of data due to noise spikes or extraneous pulses appearing on the clock inputs to the address and data register.